AMD said it was providing programmable radio SoCs to meta-platforms as part of a program to reduce the cost of building sprawling wireless networks that can handle the deluge of data from the metaverse.
The Santa Clara, Calif.-based chipmaker is offering its Xilinx-designed Zynq UltraScale RFSoC to Meta’s Evenstar program, which promotes new Open RAN technology for building 4G and 5G base stations.
AMD’s partnership with Meta follows its $49 billion acquisition of Xilinx, which was completed in February.
Everything about this base station
A base station, also known as a radio access network (RAN), is a collection of hardware modules that are typically mounted on poles or buildings and connect phones or other devices to a wireless network. The RAN includes a radio unit (RU) that contains radio frequency (RF) transceivers and other integrated circuits to convert and amplify RF signals. The radio unit is usually located near or integrated directly into the antennas of a base station.
One of the other key components of a base station is the distributed unit (DU), which houses the baseband processor that performs the L1 (or PHY) functions of the RAN protocol stack or shares the load with the RU. The final component is the central processing unit (CU), which runs inside the operator’s cloud data centers and controls many of the DUs.
According to industry analysts, base stations today are replete with proprietary interfaces, so telcos are forced to purchase all components from a single vendor in a pre-packaged hardware and software package. integrated.
Open RAN allows telecom operators to mix and match the best hardware and software for base stations instead of buying everything from Ericsson, Huawei Technologies, Nokia or other vendors. Experts warn we are years away from a completely open model for building base stations, but the Open RAN standard could give telecom operators much more flexibility and make hardware prices more competitive.
Open RAN allows flexible partitioning network functions, a concept called disaggregated RAN. AMD said the Zynq RFSoC gives telcos the flexibility to split baseband processing between radio and DUs.
Scalable SoC, Hard IP
The RU is home to a range of components, including the RF transceiver and digital front end (DFE), which is the building block that AMD is targeting with the UltraScale RFSoC family. The DFE is one of the most critical steps in the base station. It serves as a bridge between the RF transceiver and the RF chips to the baseband modem on the other side used to handle the PHY (or L1) signal processing jobs in the radio.
The DFE can reconfigure the radio’s channels in real time and perform pre-processing on the radio signals from the base station antennas, then clarify them before sending them to the baseband processor in the DU.
With its heterogeneous architecture, the RFSoC UltraScale can serve as a complete software-defined radio that can meet a range of requirements for 4G and 5G networks based on the mmWave and sub-6GHz bands.
AMD said the RFSoC UltraScale has a combination of hardened logic for RF functions while leaving a degree of programmable logic – the same type of logic at the heart of Xilinx’s FPGAs – so its customers can differentiate themselves from other telcos. .
With the ability to operate in both 4G LTE and 5G modes at the same time in a single radio, the chip features a wideband RF transceiver with eight transmit channels and eight receive channels with up to 400 MHz of bandwidth instantaneous bandwidth (IBW).
The hardware accelerators at the heart of Xilinx’s RFSoC can perform digital upconversion (DUC) and downconversion (DDC) to shift the baseband signal up or down at different frequencies. The digital-to-analog (DAC) and analog-to-digital (ADC) converters inside support a direct RF bandwidth of 7.125 GHz. Hardened logic can handle other tasks such as crest factor reduction (CFR) to reduce noise in radio transmissions.
Finally, the signal processing unit of the RFSoC manufactured by Xilinx provides resampling and other radio functionality.
Open the future of RAN
5G radios require high-end chips that not only meet the bandwidth, power, and cost-effectiveness for large-scale deployment in the field, but they must also have the flexibility to adapt to new standards. 5G such as Open RAN.
Integrating everything on a single compact chip reduces hardware power and heat dissipation. The use of hardened IP helps control costs, while programmable logic leaves the door open to design flexibility.
The large instantaneous bandwidth allows it to support carrier aggregation (CA) with up to eight carriers for each base station antenna. More data channels in the same radio help reduce system-level costs.
There is also a hardware accelerator for digital predistortion (DPD), which is widely used to increase the linearity of RF power amplifiers. It’s a soft-core processor that customers can tailor to their specific needs, AMD said.
RFSoC can be paired with a wide range of energy-efficient power amplifiers, including advanced broadband GaN power amplifiers that help increase efficiency and power density in 4G LTE and 5G RANs. Used as a millimeter wave intermediate frequency (IF) transceiver, it offers up to 1600 MHz of bandwidth.
The AMD-Meta combination builds on the efforts of other telecommunications and technology companies that support Open RAN.
Open RAN is expected to account for up to 15% of the total RAN infrastructure market by 2026, according to market research firm Dell’Oro Group.